1. Technical Field
Exemplary embodiments relate to a system on chip (SoC), more particularly, to and SOC comprising a gate contact structure.
2. Description of the Related Art
Multigate transistors have been suggested as one of the scaling technologies to increase density of a semiconductor device, in which a multichannel active pattern (or silicon body) in a fin or nanowire form is formed on a substrate, and then gates are formed on a multichannel active pattern surface.
Because the multigate transistor uses a three-dimensional channel, scaling is facilitated. Further, electric current control ability can be enhanced without having to increase lengths of the gates of the multigate transistor. Furthermore, it is possible to effectively control short channel effect (SCE) in which electric potential in channel region is influenced by the drain voltage.